View UPD754202GSA_3022193.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

the m pd754202 is a member of the 75xl series of 4-bit single-chip microcontrollers that enable data processing equivalent to that of an 8-bit microcontroller. it features expanded cpu functions compared to the 75x series and enables high-speed, low-voltage operation at 1.8 v, making it suitable for battery-driven applications. the m pd754202(a) is a higher-reliability product compared to the m pd754202. detailed function descriptions, etc., are provided in the following users manual. be sure to read it when designing. m pd754202 users manual: u11132e features ? key return reset function for keyless entry ? low-voltage operation: v dd = 1.8 to 6.0 v ? on-chip memory ? program memory (rom): 2048 8 bits ? data memory (ram) : 128 4 bits ? variable instruction execution time useful for high-speed operation and power save ? 0.95, 1.91, 3.81, 15.3 m s (at 4.19-mhz operation) ? 0.67, 1.33, 2.67, 10.7 m s (at 6.0-mhz operation) ? compact package (20-pin plastic shrink sop (300 mil, 0.65-mm pitch)) applications automotive electronics such as keyless entry units the m pd754202 and m pd754202(a) have different quality grades. unless otherwise specified, descriptions in this data sheet apply to the m pd754202. mos integrated circuit m pd754202, 754202(a) document no. u12181ej1v0ds00 (1st edition) date published may 1997 n printed in japan 4-bit single-chip microcontrollers 1997 data sheet the information in this document is subject to change without notice.
2 m pd754202, 754202(a) ordering information part number package quality grade m pd754202gs- -ba5 20-pin plastic sop (300 mil, 1.27-mm pitch) standard m pd754202gs- -gjg 20-pin plastic shrink sop (300 mil, 0.65-mm pitch) standard m pd754202gs(a)- -ba5 20-pin plastic sop (300 mil, 1.27-mm pitch) special m pd754202gs(a)- -gjg 20-pin plastic shrink sop (300 mil, 0.65-mm pitch) special remark indicates the rom code suffix. differences between m pd754202 and m pd754202(a) part number m pd754202 m pd754202(a) item quality grade standard special please refer to "quality grades on nec semiconductor devices" (document no. c11531e) published by nec corporation to know the specification of quality grade on the devices and its recommended applications.
3 m pd754202, 754202(a) function list parameter function instruction execution time ? 0.95, 1.91, 3.81, 15.3 m s (system clock: at 4.19-mhz operation) ? 0.67, 1.33, 2.67, 10.7 m s (system clock: at 6.0-mhz operation) on-chip memory rom 2048 8 bits ram 128 4 bits general-purpose register ? 4-bit manipulation: 8 4 banks ? 8-bit manipulation: 4 4 banks i/o port cmos input 4 mask option-specifiable on-chip pull-up resistor cmos input/output 9 software-specifiable on-chip pull-up resistor connection total 13 timer 4 channels ? 8-bit timer counter: 3 channels (usable as 16-bit timer counter) ? basic interval timer/watchdog timer: 1 channel bit sequential buffer (bsb) 16 bits vectored interrupt external: 1, internal: 4 test input external: 1 (key return reset function provided) system clock oscillation circuit ceramic/crystal oscillation circuit standby function stop/halt mode operating ambient temperature t a = C40 to +85 ?c supply voltage v dd = 1.8 to 6.0 v package ? 20-pin plastic sop (300 mil, 1.27-mm pitch) ? 20-pin plastic shrink sop (300 mil, 0.65-mm pitch)
4 m pd754202, 754202(a) contents 1. pin configuration (top view) .................................................................................................... 6 2. block diagram ............................................................................................................................... 7 3. pin function .................................................................................................................................... 8 3.1 port pins ...................................................................................................................................... 8 3.2 non-port pins .............................................................................................................................. 9 3.3 pin input/output circuits ......................................................................................................... 10 3.4 recommended connection of unused pins .......................................................................... 11 4. switching function between mk i mode and mk ii mode ....................................... 12 4.1 differences between mk i mode and mk ii mode .................................................................... 12 4.2 setting method of stack bank select register (sbs) ........................................................... 13 5. memory configuration ............................................................................................................14 6. peripheral hardware function ......................................................................................... 17 6.1 digital i/o port ........................................................................................................................... 17 6.2 clock generator ........................................................................................................................17 6.3 basic interval timer/watchdog timer ..................................................................................... 19 6.4 timer counter ........................................................................................................................... 20 6.5 bit sequential buffer ................................................................................................................ 24 7. interrupt function and test function ........................................................................... 25 8. standby function .......................................................................................................................27 9. reset function ............................................................................................................................ 28 9.1 configuration and operation status of reset function ........................................................ 28 9.2 watchdog flag (wdf), key return flag (krf) ...................................................................... 32 10. mask option .................................................................................................................................. 34 11. instruction sets ......................................................................................................................... 35 12. electrical specifications ...................................................................................................... 44 13. characteristic curves (reference values) ................................................................ 53 14. package drawings ...................................................................................................................... 55 15. recommended soldering conditions .................................................................................. 57
5 m pd754202, 754202(a) appendix a. m pd754202, 75f4264 function list ..................................................................... 58 appendix b. development tools .............................................................................................. 59 appendix c. related documents .............................................................................................. 62
6 m pd754202, 754202(a) 1. pin configuration (top view) ? 20-pin plastic sop (300 mil, 1.27-mm pitch) m pd754202gs- -ba5 m pd754202gs(a)- -ba5 ? 20-pin plastic shrink sop (300 mil, 0.65-mm pitch) m pd754202gs- -gjg m pd754202gs(a)- -gjg ic: internally connected (connect directly to v dd ) pin identification ic : internally connected int0 : external vectored interrupt kr4 to kr7 : key return 4 to 7 krren : key return reset enable p30 to p33 : port 3 p60 to p63 : port 6 p70 to p73 : port 7 p80 : port 8 pto0 to pto2 : programmable timer output 0 to 2 reset : reset v dd : positive power supply v ss : ground x1, x2 : system clock (ceramic/crystal) 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 reset x1 x2 v ss ic v dd p60 p61/int0 p62 p63 krren p80 p30/pto0 p31/pto1 p32/pto2 p33 p70/kr4 p71/kr5 p72/kr6 p73/kr7
7 m pd754202, 754202(a) 2. block diagram basic interval timer/watchdog timer 8-bit timer counter#0 8-bit timer counter# 1 8-bit timer counter#2 cascaded 16-bit timer counter interrupt control intbt reset intt0 tout intt1 intt2 pto0/p30 pto1/p31 pto2/p32 int0/p61 kr4/p70- kr7/p73 alu program counter program memory (rom) 2048 8 bits decode and control cy sp (8) sbs bank general reg. data memory (ram) 128 4 bits port3 4 port6 4 port7 4 port8 1 bit seq. buffer (16) p30-p33 p60-p63 p70-p73 p80 clock divider system clock generator stand by control f x /2 n x1 x2 f cpu clock ic v dd v ss reset 4 krren
8 m pd754202, 754202(a) 3. pin function 3.1 port pins pin name input/output alternate function 8-bit after reset i/o circuit function i/o type note p30 input/output pto0 C input e-b p31 pto1 p32 pto2 p33 C p60 input/output C C input f -a p61 int0 p62 C p63 C p70 input kr4 C input b -a p71 kr5 p72 kr6 p73 kr7 p80 input/output C C input f -a note circled characters indicate schmitt trigger input. programmable 4-bit input/output port (port3). this port can be specified input/output bit- wise. on-chip pull-up resistor can be specified by software in 4-bit units. programmable 4-bit input/output port (port6). this port can be specified input/output bit-wise. on-chip pull-up resistor can be specified by software in 4-bit units. noise eliminator can be selected on p61/ int0. 4-bit input port (port7). on-chip pull-up resistor can be specified bit-wise (mask option). 1-bit input/output port (port8). on-chip pull-up resistor can be specified by software.
9 m pd754202, 754202(a) 3.2 non-port pins pin name input/output alternate function after reset i/o circuit function type note pto0 output p30 timer counter output input e-b pto1 p31 pto2 p32 int0 input p61 edge detection vectored noise eliminator/ input f -a interrupt input (detected asynchronous edge is selectable) selectable noise eliminator selectable kr4 to kr7 input p70 to p73 falling edge detection testable input input b -a krren input C key return reset enable. input b when krren = high level in stop mode, reset signal is generated at falling edge of krn. x1 input C system clock oscillation crystal/ceramic C C connection pin. x2 C if using an external clock, input to x1 and reverse input to x2. reset input C system reset input (low-level active). C b -a pull-up resistor can be incorporated on-chip (mask option). ic C C internally connected. connect directly to v dd .CC v dd C C positive power supply C C v ss C C ground potential C C note circled characters indicate schmitt trigger input.
10 m pd754202, 754202(a) 3.3 pin input/output circuits the m pd754202 pin input/output circuits are shown schematically. type a type b type d type e-b type b-a type f-a v dd in p-ch n-ch data output disable n-ch p-ch in out v dd p-ch output disable data p.u.r. enable type d type a in/out v dd p.u.r. (mask option) in v dd p.u.r. p.u.r. enable p-ch in/out type d type b output disable data p.u.r. : pull-up resistor p.u.r. : pull-up resistor p.u.r. : pull-up resistor schmitt trigger input with hysteresis characteristics cmos standard input buffer push-pull output that can be placed in output high-impedance (both p-ch and n-ch off). p.u.r. v dd
11 m pd754202, 754202(a) 3.4 recommended connection of unused pins table 3-1. list of recommended connection of unused pins pin recommended connecting method p30/pto0 input state : independently connect to v ss or v dd via a resistor. p31/pto1 output state: leave open. p32/pto2 p33 p60 p61/int0 p62 p63 p70/kr4 connect to v dd . p71/kr5 p72/kr6 p73/kr7 p80 input state : independently connect to v ss or v dd via a resistor. output state: leave open. krren when this pin is connected to v dd , internal reset signal is gener- ated at the falling edge of the krn pin in the stop mode. when this pin is connected to v ss , internal reset signal is not generated even if the falling edge of krn pin is detected in the stop mode. ic connect directly to v dd .
12 m pd754202, 754202(a) 4. switching function between mk i mode and mk ii mode 4.1 differences between mk i mode and mk ii mode the m pd754202 75xl cpu has the following two modes: mk i and mk ii, either of which can be selected. the mode can be switched by bit 3 of the stack bank select register (sbs). ? mk i mode : instructions are compatible with the 75x series. can be used in the 75xl cpu with a rom capacity of up to 16 kbytes. ? mk ii mode: incompatible with 75x series. can be used in all the 75xl cpus including those products whose rom capacity is more than 16 kbytes. table 4-1. differences between mk i mode and mk ii mode mk i mode mk ii mode number of stack bytes 2 bytes 3 bytes for subroutine instructions bra !addr1 instruction not available available calla !addr1 instruction call !addr instruction 3 machine cycles 4 machine cycles callf !faddr instruction 2 machine cycles 3 machine cycles caution the mk ii mode supports a program area exceeding 16 kbytes for the 75x and 75xl series. therefore, this mode is effective for enhancing software compatibility with products that have a program area of more than 16 kbytes. the number of stack bytes (usable area) during execution of subroutine call instruc- tions increases by 1 byte per stack compared to the mk i mode when the mk ii mode is selected. however, when the call !addr and call !faddr instructions are used, the machine cycle becomes longer by 1 machine cycle. therefore, if more emphasis is placed on ram use efficiency and processing performance than on software compatibility, the mk i mode should be used.
13 m pd754202, 754202(a) 4.2 setting method of stack bank select register (sbs) switching between the mk i mode and mk ii mode can be done by the sbs. figure 4-1 shows the format. the sbs is set by a 4-bit memory manipulation instruction. when using the mk i mode, the sbs must be initialized to 1000b at the beginning of a program. when using the mk ii mode, it must be initialized to 0000b. figure 4-1. stack bank select register format sbs3 sbs2 sbs1 sbs0 3210 symbol sbs address f84h 00 0 1 0 memory bank 0 other than above setting prohibited 0 must be set in the bit 2 position. stack area specification mk ii mode mk i mode mode switching specification caution because sbs.3 is set to 1 after a reset signal is generated, the cpu operates in the mk i mode. when executing an instruction in the mk ii mode, set sbs.3 to 0 to select the mk ii mode.
14 m pd754202, 754202(a) 5. memory configuration ? program memory (rom): 2048 8 bits (0000h-07ffh) ? addresses 0000h and 0001h vector table wherein the program start address and the values set for the rbe and mbe at the time a reset signal is generated are written. reset start is possible from any address. ? addresses 0002h to 000dh vector table wherein the program start address and values set for the rbe and mbe by the vectored interrupts are written. interrupt service can start from any address. ? addresses 0020h to 007fh table area referenced by the geti instruction note . note the geti instruction realizes a 1-byte instruction on behalf of any 2-byte instruction, 3-byte instruction, or two 1-byte instructions. it is used to decrease the number of program steps. ? data memory (ram) ? data area: 128 words 4 bits (000h-07fh) ? peripheral hardware area: 128 words 4 bits (f80h-fffh)
15 m pd754202, 754202(a) figure 5-1. program memory map note can be used in mk ii mode only. remark in addition to the above, a branch can be made to an address with only the low-order 8 bits of the pc changed by means of a br pcde or br pcxa instruction. 7 6 0 mbe rbe internal reset start address (high-order 3 bits) internal reset start address (low-order 8 bits) mbe rbe intbt start address (high-order 3 bits) intbt start address (low-order 8 bits) mbe rbe int0 start address (high-order 3 bits) int0 start address (low-order 8 bits) mbe rbe intt0 start address (high-order 3 bits) intt0 start address (low-order 8 bits) mbe rbe intt1/intt2 start address (high-order 3 bits) intt1/intt2 start address (low-order 8 bits) geti instruction reference table 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000ah 000bh 000ch 000dh 0020h 007fh 0080h 07ffh callf !faddr instruction entry address branch address of br !addr brcb !caddr br bcde br bcxa bra !addr1 note call !addr calla !addr1 note instructions geti branch/call address br $addr instruction relative branch address (?5 to ?, +2 to +16) address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3
16 m pd754202, 754202(a) figure 5-2. data memory map 000h 01fh 020h 07fh 080h 0ffh f80h fffh 128 4 not incorporated 128 4 (96 4) (32 4) 0 15 general-purpose register area stack area data area static ram (128 4) peripheral hardware area data memory memory bank
17 m pd754202, 754202(a) 6. peripheral hardware function 6.1 digital i/o port the following two types of i/o ports are provided. ? cmos input (port7) : 4 ? cmos input/output (port3, 6, 8) : 9 total 13 table 6-1. types and features of digital ports port name function operation and features remarks port3 4-bit i/o can be set to input or output mode bit-wise. also used for pto0 to pto2 pins. port6 also used for int0 pin. port7 4-bit input 4-bit input only port also used for kr4 to kr7 pins. on-chip pull-up resistor can be specified by mask option bit-wise. port8 1-bit i/o can be set to input or output mode bit-wise. C 6.2 clock generator the clock generator provides the clock signals to the cpu and peripheral hardware. its configuration is shown in figure 6-1. the operation of the clock generator is set with the processor clock control register (pcc). the instruction execution time can be changed as follows. ? 0.95, 1.91, 3.81, 15.3 m s (system clock operating at 4.19 mhz) ? 0.67, 1.33, 2.67, 10.7 m s (system clock operating at 6.0 mhz)
18 m pd754202, 754202(a) figure 6-1. clock generator block diagram note instruction execution remarks 1. f x : system clock frequency 2. f = cpu clock 3. pcc: processor clock control register 4. one clock cycle (t cy ) of the cpu clock is equal to one machine cycle of the instruction. x1 x2 system clock oscillator oscillation stops 1/2 1/4 1/16 f x divider 1/4 f halt f/f s r q s r q stop f/f pcc0 pcc1 pcc2 pcc3 pcc2, pcc3 clear halt note stop note wait release signal from bt reset signal standby release signal from interrupt control circuit pcc 4 ?basic interval timer (bt) ?timer counter ?int0 noise eliminator 1/1 to 1/4096 ?cpu ?int0 noise eliminator divider selector internal bus
19 m pd754202, 754202(a) 6.3 basic interval timer/watchdog timer the basic interval timer/watchdog timer has the following functions. (a) interval timer operation to generate a reference time interrupt (b) watchdog timer operation to detect a runaway of program and reset the cpu (c) selects and counts the wait time when the standby mode is released (d) reads the contents of counting figure 6-2. basic interval timer/watchdog timer block diagram note instruction execution from clock generator f x /2 5 f x /2 7 f x /2 9 f x /2 12 mpx btm3 btm2 btm1 btm0 btm 4 set1 note internal bus 81 basic interval timer (8-bit frequency divider) clear bt wait release signal when standby is released. set clear 3 wdtm set1 note internal reset signal vectored interrupt request signal bt interrupt request flag irqbt
20 m pd754202, 754202(a) 6.4 timer counter the m pd754202 incorporates three timer counters. its configuration is shown in figures 6-3, 6-4, and 6-5. the timer counter functions are shown below. (a) programmable interval timer operation (b) square wave output of any frequency to pto0-pto2 pins (c) count value read function the timer counter can operate in the following four modes as set by the mode register. table 6-2. mode list mode channel channel 0 channel 1 channel 2 tm11 tm10 tm21 tm20 8-bit timer counter mode 0000 pwm pulse generator mode 0001 16-bit timer counter mode 1010 carrier generator mode 0011 remark : available : not available
21 m pd754202, 754202(a) figure 6-3. timer counter (channel 0) block diagram ? tm06 tm05 tm04 tm03 tm02 0 0 tm0 set1 note 8 8 8 mpx from clock generator timer operation start cp clear count register (8) t0 8 8 comparator (8) modulo register (8) tmod0 tout f/f reset toe0 port3.0 pmga bit 0 t0 enable flag p30 output latch port 3 input/output mode output buffer p30/pto0 intt0 irqt0 set signal ? ? ? ? reset irqt0 clear signal internal bus match f x /2 4 f x /2 6 f x /2 8 f x /2 10 note instruction execution caution always set bits 0 and 1 to 0 when setting data to tm0.
22 m pd754202, 754202(a) figure 6-4. timer counter (channel 1) block diagram 8 8 8 8 tm15 tm14 tm13 tm12 tm11 tm10 tm16 ? tm1 decoder mpx timer counter (channel 2) output from clock generator cp clear t1 count register (8) comparator (8) modulo register (8) tmod1 timer operation start 16-bit timer counter mode selector match reset tout f/f toe1 port3.1 pmga bit 1 t1 enable flag p31 output latch port 3 input/output mode output buffer p31/pto1 intt1 irqt1 set signal ? ? ? ? reset irqt1 clear signal timer counter (channel 2) match signal (when 16-bit timer counter mode) timer counter (channel 2) comparator (when 16-bit timer counter mode) timer counter (channel 2) reload signal internal bus f x /2 5 f x /2 6 f x /2 8 f x /2 10 f x /2 12 set1 note note instruction execution
23 m pd754202, 754202(a) figure 6-5. timer counter (channel 2) block diagram internal bus 8 8 8 8 8 8 8 tm25 tm24 tm23 tm22 tm21 tm20 tm26 ? mpx decoder from clock generator cp 16-bit timer counter mode timer operation start count register (8) comparator (8) mpx (8) match tout f/f t2 high-level period setting modulo register (8) modulo register (8) reset ? ? toe2 remc nrzb nrz ? 8 tmod2 tmodh tc2 reload overflow carrier generator mode port3.2 pmga bit 2 p32 output latch port 3 input/output mode output buffer p32/pto2 timer counter (channel 1) clock input intt2 irqt2 set signal ? ? ? ? reset irqt2 clear signal timer counter (channel 1) match signal (when 16-bit timer counter mode) timer counter (channel 1) clear signal (when 16-bit timer counter mode) timer counter (channel 1) match signal (when carrier generator mode) tm2 clear selector selector f x f x /2 f x /2 4 f x /2 6 f x /2 8 f x /2 10 set1 note 0 note instruction execution caution always set bit 7 to 0 when setting data to tc2.
24 m pd754202, 754202(a) 6.5 bit sequential buffer ....... 16 bits the bit sequential buffer (bsb) is a special data memory for bit manipulation and the bit manipulation can be easily performed by changing the address specification and bit specification in sequence, therefore it is useful when processing large data bit-wise. figure 6-6. bit sequential buffer format remarks 1. in the pmem.@l addressing, the specified bit moves corresponding to the l register. 2. in the pmem.@l addressing, the bsb can be manipulated regardless of mbe/mbs specification. address bit symbol l register l = fh l = ch l = bh l = 8h l = 7h l = 4h l = 3h l = 0h decs l incs l bsb3 bsb2 bsb1 bsb0 3210321032103210 fc3h fc2h fc1h fc0h
25 m pd754202, 754202(a) 7. interrupt function and test function the m pd754202 is provided with five types of interrupt sources and one test source to enable a variety of applications. the interrupt control circuit of the m pd754202 has the following functions. (1) interrupt function ? vectored interrupt function for hardware control, enabling/disabling the interrupt acknowledgement by the interrupt enable flag (ie ) and interrupt master enable flag (ime). ? can set any interrupt start address. ? multiple interrupts wherein the order of priority can be specified by the interrupt priority select register (ips). ? test function of interrupt request flag (irq ). an interrupt generated can be checked by software. ? release the standby mode. the interrupt to be released can be selected by the interrupt enable flag. (2) test function ? test request flag (irq2) generation can be checked by software. ? release the standby mode. the test source to be released can be selected by the test enable flag.
26 m pd754202, 754202(a) figure 7-1. interrupt control circuit block diagram internal bus interrupt enable flag (ie ) 2 4 im2 im0 note1 edge detector int0/p61 intbt intt0 intt1 intt2 irqbt irq0 irqt0 irqt1 irqt2 irq2 kr4/p70 kr7/p73 falling edge detector note 2 key return reset circuit im2 ime ips ist1 ist0 decoder vrqn priority control circuit standby release signal selector vector table address generator notes 1. noise eliminator (standby release is disabled when noise eliminator is selected.) 2. the int2 pin is not available. interrupt request flag (irq2) is set at the krn pin falling edge when im20 = 1 and im21 = 0.
27 m pd754202, 754202(a) 8. standby function in order to reduce power dissipation while a program is in standby mode, two types of standby modes (stop mode and halt mode) are provided for the m pd754202. table 8-1. operation status in standby mode item mode stop mode halt mode set instruction stop instruction halt instruction operation clock generator operation stops. only the cpu clock f halts (oscillation status continues). basic interval timer/ operation stops. operable watchdog timer bt mode : the irqbt is set in the reference time interval. wt mode: reset signal generation by bt overflow. timer counter operation stops. operable. external interrupt the int0 is not operable note . the int2 is operable at the falling edge of krn. cpu operation stops. release signal ? reset signal ? reset signal ? interrupt request signal sent from ? interrupt request signal sent from interrupt enabled hardware interrupt enabled hardware ? system reset signal (key return reset) generated by krn falling edge when krren pin = 1. note can operate only when the noise eliminator is not used (im02 = 1) by bit 2 of the edge detection mode register (im0).
28 m pd754202, 754202(a) 9. reset function 9.1 configuration and operation status of reset function there are three kinds of reset input: the external reset signal (reset), the reset signal sent from the basic interval/watchdog timer, and the reset signal generated by a falling edge signal from krn in the stop mode. when any of these reset signals is input, an internal reset signal is generated. the configuration is shown in figure 9-1. figure 9-1. configuration of reset function v dd mask option krren reset q r s q s r q s r instruction stop mode krf wdf watchdog timer overflow internal reset signal instruction v dd mask option p70/kr4 p71/kr5 p72/kr6 p73/kr7 internal bus falling edge detector interrupt one-shot pulse generator
29 m pd754202, 754202(a) the reset signal generation initializes each hardware as listed in table 9-1. figure 9-2 shows the timing chart of the reset operation. figure 9-2. reset operation by reset signal generation note the following 2 time modes can be specified with mask option. 2 17 /f x (21.8 ms: at 6.0-mhz operation, 31.3 ms: at 4.19-mhz operation) 2 15 /f x (5.46 ms: at 6.0-mhz operation, 7.81 ms: at 4.19-mhz operation) operation mode or standby mode wait note reset signal generated operation mode halt mode internal reset operation
30 m pd754202, 754202(a) table 9-1. hardware status after reset (1/3) hardware reset signal generation reset signal generation in the standby mode in operation program counter (pc) sets the low-order 3 bits of sets the low-order 3 bits of program memorys address program memorys address 0000h to the pc10-pc8 and the 0000h to the pc10-pc8 and the contents of address 0001h to contents of address 0001h to the pc7-pc0. the pc7-pc0. psw carry flag (cy) held undefined skip flag (sk0-sk2) 0 0 interrupt status flag (ist0, ist1) 0 0 bank enable flag (mbe, rbe) sets the bit 6 of program sets the bit 6 of program memorys address 0000h to memorys address 0000h to the rbe and bit 7 to the mbe. the rbe and bit 7 to the mbe. stack pointer (sp) undefined undefined stack bank select register (sbs) 1000b 1000b data memory (ram) held undefined general-purpose register (x, a, h, l, d, e, b, c) held undefined bank select register (mbs, rbs) 0, 0 0, 0 basic interval counter (bt) undefined undefined timer/watchdog mode register (btm) 0 0 timer watchdog timer enable flag (wdtm) 00 timer counter counter (t0) 0 0 (t0) modulo register (tmod0) ffh ffh mode register (tm0) 0 0 toe0, tout f/f 0, 0 0, 0 timer counter counter (t1) 0 0 (t1) modulo register (tmod1) ffh ffh mode register (tm1) 0 0 toe1, tout f/f 0, 0 0, 0 timer counter counter (t2) 0 0 (t2) modulo register (tmod2) ffh ffh high-level period setting modulo ffh ffh register (tmod2h) mode register (tm2) 0 0 toe2, tout f/f 0, 0 0, 0 remc, nrz, nrzb 0, 0, 0 0, 0, 0
31 m pd754202, 754202(a) table 9-1. hardware status after reset (2/3) hardware reset signal generation reset signal generation in the standby mode in operation clock generator processor clock control register (pcc) 0 0 interrupt interrupt request flag (irq ) reset (0) reset (0) function interrupt enable flag (ie )0 0 interrupt master enable flag (ime) 0 0 interrupt priority selection register (ips) 00 int0, 2 mode registers (im0, im2) 0, 0 0, 0 digital port output buffer off off output latch cleared (0) cleared (0) i/o mode registers (pmga, pmgc) 0 0 pull-up resistor setting register (poga, pogb) 00 bit sequential buffer (bsb0-bsb3) held undefined table 9-1. hardware status after reset (3/3) reset signal reset signal reset signal reset signal hardware generation by key generation in the generation by wdt generation during return reset standby mode during operation operation watchdog flag (wdf) hold the previous status 010 key return flag (krf) 1 0 hold the previous status 0
32 m pd754202, 754202(a) 9.2 watchdog flag (wdf), key return flag (krf) the wdf is set by a watchdog timer overflow signal, and the krf is set by a reset signal generated by the krn pins. as a result, by checking the contents of wdf and krf, it is possible to know what kind of reset signal is generated. as the wdf and krf are cleared only by external signal or instruction execution, if once these flags are set, they are not cleared until an external signal is generated or a clear instruction is executed. check and clear the contents of wdf and krf after reset start operation by executing sktclr instruction and so on. table 9-2 lists the contents of wdf and krf corresponding to each signal. figure 9-3 shows the wdf operation in generating each signal, and figure 9-4 shows the krf operation in generating each signal. table 9-2. wdf and krf contents correspond to each signal external reset reset signal reset signal wdf clear krf clear hardware signal generation generation by watch- generation by the instruction instruction dog timer overflow krn input execution execution watchdog flag (wdf) 0 1 hold 0 hold key return flag (krf) 0 hold 1 hold 0 figure 9-3. wdf operation in generating each signal external reset wdf operation mode reset signal generation by watchdog timer overflow external reset signal generation wdf clear instruction execution operation mode halt mode operation mode halt mode operation mode halt mode operation mode internal reset operation internal reset operation internal reset operation reset signal generation by watchdog timer overflow
33 m pd754202, 754202(a) figure 9-4. krf operation in generating each signal external reset krf operation mode operation mode halt mode operation mode internal reset operation stop mode internal reset operation internal reset operation halt mode operation mode stop mode halt mode operation mode stop instruction execution reset signal generation by the krn input external reset signal generation stop instruction execution krf clear instruction execution reset signal generation by the krn input
34 m pd754202, 754202(a) 10. mask option the m pd754202 has the following mask options: ? mask option of p70/kr4 through p73/kr7 pull-up resistors can be connected to these pins. (1) no pull-up resistor connection (2) connection of a 30-k w (typ.) pull-up resistor in 1-bit units. (3) connection of a 100-k w (typ.) pull-up resistor in 1-bit units. ? mask option of reset pin pull-up resistors can be connected to these pins. (1) no pull-up resistor connection (2) connection of a 100-k w (typ.) pull-up resistor. ? standby function mask option the wait time after reset signal can be selected. (1) 2 17 /f x (21.8 ms: f x = 6.0-mhz operation, 31.3 ms: f x = 4.19-mhz operation) (2) 2 15 /f x (5.46 ms: f x = 6.0-mhz operation, 7.81 ms: f x = 4.19-mhz operation)
35 m pd754202, 754202(a) 11. instruction sets (1) expression formats and description methods of operands the operand is described in the operand column of each instruction in accordance with the description method for the operand expression format of the instruction. for details, refer to ra75x assembler package users manual language (eeu-1363) . if there are several elements, one of them is selected. capital letters and the + and C symbols are key words and are described as they are. for immediate data, appropriate numbers and labels are described. instead of the labels such as mem, fmem, pmem, and bit, the symbols of the register flags can be described. however, there are restrictions in the labels that can be described for fmem and pmem. for details, see m pd754202 users manual (u11132e) . expression description method format reg x, a, b, c, d, e, h, l reg1 x, b, c, d, e, h, l rp xa, bc, de, hl rp1 bc, de, hl rp2 bc, de rp' xa, bc, de, hl, xa', bc', de', hl' rp'1 bc, de, hl, xa', bc', de', hl' rpa hl, hl+, hlC, de, dl rpa1 de, dl n4 4-bit immediate data or label n8 8-bit immediate data or label mem 8-bit immediate data or label note bit 2-bit immediate data or label fmem fb0h-fbfh, ff0h-fffh immediate data or label pmem fc0h-fffh immediate data or label addr 0000h-07ffh immediate data or label addr1(only in 0000h-07ffh immediate data or label mk ii mode) caddr 12-bit immediate data or label faddr 11-bit immediate data or label taddr 20h-7fh immediate data (where bit0 = 0) or label portn port3, 6, 7, 8 ie iebt, iet0-iet2, ie0, ie2 rbn rb0-rb3 mbn mb0, mb15 note mem can be only used for even address in 8-bit data processing.
36 m pd754202, 754202(a) (2) legend in explanation of operation a : a register; 4-bit accumulator b : b register c : c register d : d register e : e register h : h register l : l register x : x register xa : xa register pair; 8-bit accumulator bc : bc register pair de : de register pair hl : hl register pair xa : xa extended register pair bc : bc extended register pair de : de extended register pair hl : hl extended register pair pc : program counter sp : stack pointer cy : carry flag; bit accumulator psw : program status word mbe : memory bank enable flag rbe : register bank enable flag portn : port n (n = 3, 6, 7, 8) ime : interrupt master enable flag ips : interrupt priority selection register ie : interrupt enable flag rbs : register bank selection register mbs : memory bank selection register pcc : processor clock control register . : separation between address and bit ( ) : the contents addressed by h : hexadecimal data
37 m pd754202, 754202(a) (3) explanation of symbols under addressing area column *1 mb = mbe?mbs (mbs = 0, 15) *2 mb = 0 *3 mbe = 0 : mb = 0 (000h-07fh) mb = 15 (f80h-fffh) data memory addressing mbe = 1 : mb = mbs (mbs = 0, 15) *4 mb = 15, fmem = fb0h-fbfh, ff0h-fffh *5 mb = 15, pmem = fc0h-fffh *6 addr = 0000h-07ffh *7 addr = (current pc) C 15 to (current pc) C 1 (current pc) + 2 to (current pc) + 16 addr1 = (current pc) C 15 to (current pc) C 1 (current pc) + 2 to (current pc) + 16 program memory addressing *8 caddr = 0000h-07ffh *9 faddr = 0000h-07ffh *10 taddr = 0020h-007fh *11 addr1 = 0000h-07ffh remarks 1. mb indicates memory bank that can be accessed. 2. in *2, mb = 0 independently of how mbe and mbs are set. 3. in *4 and *5, mb = 15 independently of how mbe and mbs are set. 4. *6 to *11 indicate the areas that can be addressed. (4) explanation of number of machine cycles column s denotes the number of machine cycles required by skip operation when a skip instruction is executed. the value of s varies as follows. ? when no skip is made: s = 0 ? when the skipped instruction is a 1- or 2-byte instruction: s = 1 ? when the skipped instruction is a 3-byte instruction note : s = 2 note 3-byte instruction: br !addr, bra !addr1, call !addr, or calla !addr1 instruction caution the geti instruction is skipped in one machine cycle. one machine cycle is equal to one cycle of the cpu clock (= t cy ); time can be selected from among four types by setting pcc.
38 m pd754202, 754202(a) instruction number number addressing mnemonic operand of machine operation skip condition group of bytes cycles area transfer mov a, #n4 1 1 a n4 string effect a instruction reg1, #n4 2 2 reg1 n4 xa, #n8 2 2 xa n8 string effect a hl, #n8 2 2 hl n8 string effect b rp2, #n8 2 2 rp2 n8 a, @hl 1 1 a (hl) *1 a, @hl+ 1 2+s a (hl), then l l+1 *1 l = 0 a, @hlC 1 2+s a (hl), then l lC1 *1 l = fh a, @rpa1 1 1 a (rpa1) *2 xa, @hl 2 2 xa (hl) *1 @hl, a 1 1 (hl) a*1 @hl, xa 2 2 (hl) xa *1 a, mem 2 2 a (mem) *3 xa, mem 2 2 xa (mem) *3 mem, a 2 2 (mem) a*3 mem, xa 2 2 (mem) xa *3 a, reg 2 2 a reg xa, rp' 2 2 xa rp' reg1, a 2 2 reg1 a rp'1, xa 2 2 rp'1 xa xch a, @hl 1 1 a (hl) *1 a, @hl+ 1 2+s a (hl), then l l+1 *1 l = 0 a, @hlC 1 2+s a (hl), then l lC1 *1 l = fh a, @rpa1 1 1 a (rpa1) *2 xa, @hl 2 2 xa (hl) *1 a, mem 2 2 a (mem) *3 xa, mem 2 2 xa (mem) *3 a, reg1 1 1 a reg1 xa, rp' 2 2 xa rp' table movt xa, @pcde 1 3 xa (pc 10C8 +de) rom reference instructions xa, @pcxa 1 3 xa (pc 10C8 +xa) rom xa, @bcde 1 3 xa (bcde) rom note *6 xa, @bcxa 1 3 xa (bcxa) rom note *6 note 0 must be set to the b register.
39 m pd754202, 754202(a) instruction number number addressing mnemonic operand of machine operation skip condition group of bytes cycles area bit transfer mov1 cy, fmem.bit 2 2 cy (fmem.bit) *4 instructions cy, pmem.@l 2 2 cy (pmem 7C2 +l 3C2 .bit(l 1C0 )) *5 cy, @h+mem.bit 2 2 cy (h+mem 3C0 .bit) *1 fmem.bit, cy 2 2 (fmem.bit) cy *4 pmem.@l, cy 2 2 (pmem 7C2 +l 3C2 .bit(l 1C0 )) cy *5 @h+mem.bit, cy 2 2 (h+mem 3C0 .bit) cy *1 operation adds a, #n4 1 1+s a a+n4 carry instructions xa, #n8 2 2+s xa xa+n8 carry a, @hl 1 1+s a a+(hl) *1 carry xa, rp' 2 2+s xa xa+rp' carry rp'1, xa 2 2+s rp'1 rp'1+xa carry addc a, @hl 1 1 a, cy a+(hl)+cy *1 xa, rp' 2 2 xa, cy xa+rp'+cy rp'1, xa 2 2 rp'1, cy rp'1+xa+cy subs a, @hl 1 1+s a aC(hl) *1 borrow xa, rp' 2 2+s xa xaCrp' borrow rp'1, xa 2 2+s rp'1 rp'1Cxa borrow subc a, @hl 1 1 a, cy aC(hl)Ccy *1 xa, rp' 2 2 xa, cy xaCrp'Ccy rp'1, xa 2 2 rp'1, cy rp'1CxaCcy and a, #n4 2 2 a a ? n4 a, @hl 1 1 a a ? (hl) *1 xa, rp' 2 2 xa xa ? rp' rp'1, xa 2 2 rp'1 rp'1 ? xa or a, #n4 2 2 a a M n4 a, @hl 1 1 a a M (hl) *1 xa, rp' 2 2 xa xa M rp' rp'1, xa 2 2 rp'1 rp'1 M xa xor a, #n4 2 2 a a v n4 a, @hl 1 1 a a v (hl) *1 xa, rp' 2 2 xa xa v rp' rp'1, xa 2 2 rp'1 rp'1 v xa accumulator rorc a 1 1 cy a 0 , a 3 cy, a nC1 a n manipulation instructions not a 2 2 a a
40 m pd754202, 754202(a) instruction number number addressing mnemonic operand of machine operation skip condition group of bytes cycles area increment incs reg 1 1+s reg reg+1 reg = 0 and decrement rp1 1 1+s rp1 rp1+1 rp1 = 00h instructions @hl 2 2+s (hl) (hl)+1 *1 (hl) = 0 mem 2 2+s (mem) (mem)+1 *3 (mem) = 0 decs reg 1 1+s reg regC1 reg = fh rp' 2 2+s rp' rp'C1 rp' = ffh comparison ske reg, #n4 2 2+s skip if reg = n4 reg = n4 instruction @hl, #n4 1 2+s skip if (hl) = n4 *1 (hl) = n4 a, @hl 2 1+s skip if a = (hl) *1 a = (hl) xa, @hl 2 2+s skip if xa = (hl) *1 xa = (hl) a, reg 2 2+s skip if a = reg a = reg xa, rp' 2 2+s skip if xa = rp' xa = rp' carry flag set1 cy 1 1 cy 1 manipulation instruction clr1 cy 1 1 cy 0 skt cy 1 1+s skip if cy = 1 cy = 1 not1 cy 1 1 cy cy memory bit set1 mem.bit 2 2 (mem.bit) 1*3 manipulation instructions fmem.bit 2 2 (fmem.bit) 1*4 pmem.@l 2 2 (pmem 7C2 +l 3C2 .bit(l 1C0 )) 1*5 @h+mem.bit 2 2 (h+mem 3C0 .bit) 1*1 clr1 mem.bit 2 2 (mem.bit) 0*3 fmem.bit 2 2 (fmem.bit) 0*4 pmem.@l 2 2 (pmem 7C2 +l 3C2 .bit(l 1C0 )) 0*5 @h+mem.bit 2 2 (h+mem 3C0 .bit) 0*1 skt mem.bit 2 2+s skip if (mem.bit) = 1 *3 (mem.bit) = 1 fmem.bit 2 2+s skip if (fmem.bit) = 1 *4 (fmem.bit) = 1 pmem.@l 2 2+s skip if (pmem 7C2 +l 3C2 .bit(l 1C0 )) = 1 *5 (pmem.@l) = 1 @h+mem.bit 2 2+s skip if (h+mem 3C0 .bit) = 1 *1 (@h+mem.bit) = 1 skf mem.bit 2 2+s skip if (mem.bit) = 0 *3 (mem.bit) = 0 fmem.bit 2 2+s skip if (fmem.bit) = 0 *4 (fmem.bit) = 0 pmem.@l 2 2+s skip if (pmem 7C2 +l 3C2 .bit(l 1C0 )) = 0 *5 (pmem.@l) = 0 @h+mem.bit 2 2+s skip if (h+mem 3C0 .bit) = 0 *1 (@h+mem.bit) = 0
41 m pd754202, 754202(a) instruction number number addressing mnemonic operand of machine operation skip condition group of bytes cycles area memory bit sktclr fmem.bit 2 2+s skip if (fmem.bit) = 1 and clear *4 (fmem.bit) = 1 manipulation instructions pmem.@l 2 2+s skip if (pmem 7C2 +l 3C2 .bit(l 1C0 )) = 1 and clear *5 (pmem.@l) = 1 @h+mem.bit 2 2+s skip if (h+mem 3C0 .bit) = 1 and clear *1 (@h+mem.bit) = 1 and1 cy, fmem.bit 2 2 cy cy ? (fmem.bit) *4 cy, pmem.@l 2 2 cy cy ? (pmem 7C2 +l 3C2 .bit(l 1C0 )) *5 cy, @h+mem.bit 2 2 cy cy ? (h+mem 3C0 .bit) *1 or1 cy, fmem.bit 2 2 cy cy M (fmem.bit) *4 cy, pmem.@l 2 2 cy cy M (pmem 7C2 +l 3C2 .bit(l 1C0 )) *5 cy, @h+mem.bit 2 2 cy cy M (h+mem 3C0 .bit) *1 xor1 cy, fmem.bit 2 2 cy cy v (fmem.bit) *4 cy, pmem.@l 2 2 cy cy v (pmem 7C2 +l 3C2 .bit(l 1C0 )) *5 cy, @h+mem.bit 2 2 cy cy v (h+mem 3C0 .bit) *1 branch br note 1 addr C C pc 10C0 addr *6 instructions select appropriate instruction among br !addr, brcb !caddr, and br $addr according to the assembler being used. addr1 C C pc 10-0 addr1 *11 select appropriate instruction among br !addr, bra !addr1, brcb !caddr, and br $addr1 according to the assembler being used. !addr 3 3 pc 10C0 addr *6 $addr 1 2 pc 10C0 addr *7 $addr1 1 2 pc 10C0 addr1 pcde 2 3 pc 10C0 pc 10-8 +de pcxa 2 3 pc 10C0 pc 10-8 +xa bcde 2 3 pc 10C0 bcde note 2 *6 bcxa 2 3 pc 10C0 bcxa note 2 *6 bra note 1 !addr1 3 3 pc 10C0 addr1 *11 brcb !caddr 2 2 pc 10C0 caddr 10C0 *8 notes 1. the above operations in the shaded boxes can be performed only in the mk ii mode. the other operations can be performed only in the mk i mode. 2. 0 must be set to the b register.
42 m pd754202, 754202(a) instruction number number addressing mnemonic operand of machine operation skip condition group of bytes cycles area subroutine calla note !addr1 3 3 (spC2) , , mbe, rbe *11 stack control (spC6) (spC3) (spC4) 0, pc 10C0 instructions (spC5) 0, 0, 0, 0 pc 10C0 addr1, sp spC6 call note !addr 3 3 (spC3) mbe, rbe, 0, 0 *6 (spC4) (spC1) (spC2) 0, pc 10C0 pc 10C0 addr, sp spC4 4 (spC2) , , mbe, rbe (spC6) (spC3) (spC4) 0, pc 10C0 (spC5) 0, 0, 0, 0 pc 10C0 addr, sp spC6 callf note !faddr 2 2 (spC3) mbe, rbe, 0, 0 *9 (spC4) (spC1) (spC2) 0, pc 10C0 pc 10C0 0+faddr, sp spC4 3 (spC2) , , mbe, rbe (spC6) (spC3) (spC4) 0, pc 10C0 (spC5) 0, 0, 0, 0 pc 10C0 0+faddr, sp spC6 ret note 13pc 10C0 (sp) 2C0 (sp+3) (sp+2) mbe, rbe, 0, 0 (sp+1), sp sp+4 , , mbe, rbe (sp+4) 0, 0, 0, 0, (sp+1) pc 10C0 (sp) 2C0 (sp+3) (sp+2), sp sp+6 rets note 1 3+s mbe, rbe, 0, 0 (sp+1) unconditional pc 10C0 (sp) 2C0 (sp+3) (sp+2) sp sp+4 then skip unconditionally 0, 0, 0, 0 (sp+1) pc 10C0 (sp) 2C0 (sp+3) (sp+2) , , mbe, rbe (sp+4) sp sp+6 then skip unconditionally reti note 1 3 mbe, rbe, 0, 0 (sp+1) pc 10C0 (sp) 2C0 (sp+3) (sp+2) psw (sp+4) (sp+5), sp sp+6 0, 0, 0, 0 (sp+1) pc 10C0 (sp) 2C0 (sp+3) (sp+2) psw (sp+4) (sp+5), sp sp+6 push rp 1 1 (spC1) (spC2) rp, sp spC2 bs 2 2 (spC1) mbs, (spC2) rbs, sp spC2 pop rp 1 1 rp (sp+1) (sp), sp sp+2 bs 2 2 mbs (sp+1), rbs (sp), sp sp+2 note the above operations in the shaded boxes can be performed only in the mk ii mode. the other operations can be performed only in the mk i mode.
43 m pd754202, 754202(a) instruction number number addressing mnemonic operand of machine operation skip condition group of bytes cycles area interrupt ei 2 2 ime (ips.3) 1 control instructions ie 22ie 1 di 2 2 ime (ips.3) 0 ie 22ie 0 input/output in note 1 a, portn 2 2 a portn (n = 3, 6, 7, 8) instructions out note 1 portn, a 2 2 portn a (n = 3, 6, 8) cpu control halt 2 2 set halt mode (pcc.2 1) instructions stop 2 2 set stop mode (pcc.3 1) nop 1 1 no operation special sel rbn 2 2 rbs n (n = 0-3) instructions mbn 2 2 mbs n (n = 0, 15) geti notes 2, 3 taddr 1 3 ? when tbr instruction *10 pc 10C0 (taddr) 2C0 + (taddr+1) ? when tcall instruction (spC4) (spC1) (spC2) 0, pc 10C0 (spC3) mbe, rbe, 0, 0 pc 10C0 (taddr) 2C0 + (taddr+1) sp spC4 ? when instruction other than tbr and depending on tcall instructions the reference (taddr) (taddr+1) instruction is executed. instruction 3 ? when tbr instruction *10 pc 10C0 (taddr) 2C0 + (taddr+1) 4 ? when tcall instruction (spC6) (spC3) (spC4) pc 10C0 (spC5) 0, 0, 0, 0 (spC2) , , mbe, rbe pc 10C0 (taddr) 2C0 + (taddr+1) sp spC6 3 ? when instruction other than tbr and depending on tcall instructions the reference (taddr) (taddr+1) instruction is executed. instruction notes 1. while the in instruction and out instruction are being executed, mbs must be set to 0, or mbe must be set to 1 and mbs must be set to 15. 2. the tbr and tcall instructions are the table definition assembler pseudo instructions of the geti instruction. 3. the above operations in the shaded boxes can be performed only in the mk ii mode. the other operations can be performed only in the mk i mode. CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC CCCCCCCCCCCCC CCCCCCCCCCCCC CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC CCCC CCCCCCCCCCCCC CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC CCCC CCCCCCCCCCCCC
44 m pd754202, 754202(a) 12. electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol test conditions ratings unit supply voltage v dd C0.3 to +7.0 v input voltage v i C0.3 to v dd + 0.3 v output voltage v o C0.3 to v dd + 0.3 v output current, high i oh per pin pins except p32 C10 ma only p32 C20 ma all pins total C30 ma output current, low i ol per pin 20 ma all pins total 90 ma operating ambient t a C40 to +85 c temperature storage temperature t stg C65 to +150 c caution if any of the parameters exceeds the absolute maximum ratings, even momentarily, the quality of the product may be impaired. the absolute maximum ratings are values that may physically damage the products. be sure to use the products within the ratings. capacitance (t a = 25 c, v dd = 0 v) parameter symbol test conditions min. typ. max. unit input capacitance c in f = 1 mhz 15 pf output capacitance c out unmeasured pins returned to 0 v 15 pf i/o capacitance c io 15 pf
45 m pd754202, 754202(a) x1 x2 x1 x2 c1 c2 x1 x2 c1 c2 system clock oscillator characteristics (t a = e40 to +85 c, v dd = 1.8 to 6.0 v) resonator recommended constant parameter testing conditions min. typ. max. unit ceramic oscillation 1.0 6.0 note 2 mhz resonator frequency (f x ) note 1 oscillation after v dd reaches min. 4 ms stabilization value of oscillation time note 3 voltage range crystal oscillation 1.0 6.0 note 2 mhz resonator frequency(f x ) note 1 oscillation v dd = 4.5 to 6.0 v 10 ms stabilization time note 3 30 ms external x1 input 1.0 6.0 note 2 mhz clock frequency (f x ) note 1 x1 input high- and 83.3 500 ns low-level widths (t xh , t xl ) notes 1. only the oscillator characteristics are shown. for the instruction execution time, refer to ac charac- teristics . 2. if the oscillation frequency is 4.19 mhz < f x 6.0 mhz at 1.8 v v dd < 2.7 v, set the processor clock control register (pcc) to a value other than 0011. if the pcc is set to 0011, the rated machine cycle time of 0.95 m s is not satisfied. 3. the oscillation stabilization time is the time required for oscillation to stabilize after application of v dd , or after the stop mode has been released. caution when using the oscillation circuit of the system clock, wire the portion enclosed in dotted lines in the figures as follows to avoid adverse influences on the wiring capacitance: ? keep the wire length as short as possible. ? do not cross other signal lines. ? do not route the wiring in the vicinity of lines though which a high fluctuating current flows. ? always keep the ground point of the capacitor of the oscillation circuit as the same potential as v ss . ? do not connect the power source pattern through which a high current flows. ? do not extract signals from the oscillation circuit.
46 m pd754202, 754202(a) recommended circuit constants ceramic resonator (t a = e20 to +80 ?c) circuit constant (pf) oscillation voltage manufacturer product frequency range (v dd ) remark (mhz) c1 c2 min.(v) max.(v) murata mfg. csb1000j note 1.0 100 100 2.0 6.0 rd = 2.2 k w co., ltd. csa2.00mg040 2.0 100 100 C cst2.00mg040 C C capacitor incorporated csa4.00mg 4.0 30 30 C cst4.00mgw C C capacitor incorporated csa4.00mgu 30 30 1.8 C cst4.00mgwu C C capacitor incorporated csa4.19mg 4.19 30 30 2.0 C cst4.19mgw C C capacitor incorporated csa4.19mgu 30 30 1.8 C cst4.19mgwu C C capacitor incorporated csa6.00mg 6.0 30 30 2.9 C cst6.00mgw C C capacitor incorporated csa6.00mgu 30 30 2.4 C cst6.00mgwu C C capacitor incorporated kyocera corp. kbr-1000f/y 1.0 100 100 1.8 6.0 C kbr-2.0ms 2.0 68 68 2.0 kbr-4.19mkc 4.19 C C 1.8 capacitor incorporated kbr-4.19msb 33 33 C pbrc4.19a pbrc4.19b C C capacitor incorporated kbr-6.0mkc 6.0 kbr-6.0msb 33 33 C pbrc6.00a pbrc6.00b C C capacitor incorporated note if using muratas csb1000j (1.0 mhz) as the ceramic resonator, a limited resistor (rd = 2.2 k w ) is required (see figure below). if using any other recommended resonator, no limited resistor is needed. x1 x2 c1 c2 rd csb1000j caution the oscillation circuit constants and oscillation voltage range indicate conditions for stable oscillation, but do not guarantee oscillation frequency accuracy. if oscillation frequency accuracy is required for actual circuits, it is necessary to adjust the oscillation frequency of the resonator in the circuit. please inquire directly to the maker of the resonator for data as needed.
47 m pd754202, 754202(a) dc characteristics (t a = e40 to +85 ?c, v dd = 1.8 to 6.0 v) parameter symbol conditions min. typ. max. unit high-level output current i oh per pin pins except p32 C5 ma only p32, C7 C15 ma v dd = 3.0 v, v oh = v dd C2.0 v all pins total C20 ma low-level output current i ol per pin 15 ma all pins total 45 ma high-level input voltage v ih1 port 3 2.7 v v dd 6.0 v 0.7 v dd v dd v 1.8 v v dd < 2.7 v 0.9 v dd v dd v v ih2 ports 6-8, krren, 2.7 v v dd 6.0 v 0.8 v dd v dd v reset 1.8 v v dd < 2.7 v 0.9 v dd v dd v v ih3 x1 v dd C0.1 v dd v low-level input voltage v il1 port 3 2.7 v v dd 6.0 v 0 0.3 v dd v 1.8 v v dd < 2.7 v 0 0.1 v dd v v il2 ports 6-8, krren, 2.7 v v dd 6.0 v 0 0.2 v dd v reset 1.8 v v dd < 2.7 v 0 0.1 v dd v v il3 x1 0 0.1 v high-level output voltage v oh v dd = 4.5 to 6.0 v, i oh = C1.0 ma v dd C1.0 v v dd = 1.8 to 6.0 v, i oh = C100 m av dd C0.5 v low-level output voltage v ol v dd = 4.5 to 6.0 v port 3, i ol = 15 ma 0.6 2.0 v ports 6, 8, 0.4 v i ol = 1.6 ma v dd = 1.8 to 6.0 v, i ol = 400 m a 0.5 v high-level input leak i lih1 v in = v dd pins except x1 3.0 m a current i lih2 x1 20 m a low-level input leak i lil1 v in = 0 v pins except x1 C3.0 m a current i lil2 x1 C20 m a high-level output i loh v out = v dd 3.0 m a leak current low-level output i lol v out = 0 v C3.0 m a leak current on-chip pull-up resistance r l1 v in = 0 v ports 3, 6, 8 50 100 200 k w r l2 port 7 (mask option) 15 30 60 k w 50 100 200 k w reset (mask option) 50 100 200 k w
48 m pd754202, 754202(a) dc characteristics (t a = e40 to +85 c, v dd = 1.8 to 6.0 v) parameter symbol test conditions min. typ. max. unit supply current note 1 i dd1 4.19 mhz v dd = 5.0 v 10 % note 2 1.5 5.0 ma crystal resonator v dd = 3.0 v 10 % note 3 0.23 1.0 ma i dd2 c1 = c2 = 22 pf halt v dd = 5.0 v 10 % 0.64 3.0 ma mode v dd = 3.0 v 10 % 0.20 0.9 ma i dd3 x1 = 0 v v dd = 1.8 to 6.0 v 5 m a stop t a = 25 c1 m a mode v dd = 3.0 v 10 % 0.1 3 m a t a = C40 to 0.1 1 m a +40 c notes 1. does not include current fed to on-chip pull-up resistor. 2. when processor clock control register (pcc) is set to 0011, during high-speed mode. 3. when pcc is set to 0000, during low-speed mode.
49 m pd754202, 754202(a) 0.5 01 2 3 4 5 6 1 2 3 4 5 6 60 64 supply voltage v dd [v] (during system clock operation) t cy vs v dd operation guaranteed range cycle time t cy [ s] m ac characteristics (t a = e40 to +85 c, v dd = 1.8 to 6.0 v) parameter symbol test conditions min. typ. max. unit cpu clock cycle time note 1 t cy when system 2.7 v v dd 6.0 v 0.67 64.0 m s (minimum instruction execution clock is used time = 1 machine cycle) 1.8 v v dd < 2.7 v 0.95 64.0 m s interrupt input high- and t inth , t intl int0 im02 = 0 note 2 m s low-level widths im02 = 1 10 m s kr4-kr7 10 m s reset low-level width t rsl 10 m s notes 1. the cpu clock ( f ) cycle time (minimum instruction execution time) is determined by the oscillation frequency of the con- nected resonator (and external clock) and the processor clock control register (pcc). the figure on the right shows the cycle time t cy characteristics against the supply voltage v dd when the system clock is used. 2. 2t cy or 128/fx depending on the setting of the interrupt mode register (im0).
50 m pd754202, 754202(a) t xl t xh 1/f x v dd e 0.1 v 0.1 v x1 input v ih (min.) v il (max.) v ih (min.) v il (max.) v oh (min.) v ol (max.) v oh (min.) v ol (max.) ac timing test points (excluding x1 input) clock timing interrupt input timing reset input timing int0, kr4-7 t intl t inth reset t rsl
51 m pd754202, 754202(a) data memory stop mode low-supply voltage data retention characteristics (t a = e40 to +85 c) parameter symbol test conditions min. typ. max. unit release signal set time t srel 0 m s oscillation stabilization t wait release by reset note 2 ms wait time note 1 release by interrupt request note 3 ms notes 1. the oscillation stabilization wait time is the time during which the cpu operation is stopped to avoid unstable operation at oscillation start. 2. 2 17 /fx and 2 15 /fx can be selected with mask option. 3. depends on setting of basic interval timer mode register (btm) (see table below). btm3 btm2 btm1 btm0 wait time when f x = 4.19 mhz when f x = 6.0 mhz C0002 20 /f x (approx. 250 ms) 2 20 /f x (approx. 175 ms) C0112 17 /f x (approx. 31.3 ms) 2 17 /f x (approx. 21.8 ms) C1012 15 /f x (approx. 7.81 ms) 2 15 /f x (approx. 5.46 ms) C1112 13 /f x (approx. 1.95 ms) 2 13 /f x (approx. 1.37 ms) data retention timing (on releasing stop mode by reset) stop mode data retention mode execution of stop instruction t wait t srel halt mode operation mode v dd reset internal reset operation
52 m pd754202, 754202(a) data retention timing (standby release signal: on releasing stop mode by interrupt signal) stop mode data retention mode execution of stop instruction v dd standby release signal (interrupt request) t wait t srel halt mode operation mode
53 m pd754202, 754202(a) 13. characteristic curves (reference values) i dd vs v dd (system clock: 6.0-mhz crystal resonator) 012345678 0.001 0.005 0.01 0.05 0.1 0.5 1.0 5.0 10 x1 x2 6.0 mhz 22 pf 22 pf pcc = 0011 pcc = 0010 pcc = 0001 pcc = 0000 halt mode system clock crystal resonator supply voltage v dd (v) supply current i dd (ma) (t a = 25 ?c)
54 m pd754202, 754202(a) i dd vs v dd (system clock: 4.19-mhz crystal resonator) 012345678 0.001 0.005 0.01 0.05 0.1 0.5 1.0 5.0 10 system clock halt mode x1 x2 4.19 mhz 22 pf 22 pf pcc = 0011 pcc = 0010 pcc = 0001 pcc = 0000 crystal resonator supply voltage v dd (v) supply current i dd (ma) (t a = 25 ?c)
55 m pd754202, 754202(a) 14. package drawings 20 pin plastic sop (300 mil) item millimeters inches a b c e f g h i j 13.00 max. 1.27 (t.p.) 1.8 max. 1.55 7.70.3 0.78 max. 0.12 1.1 5.6 m 0.10.1 n 0.512 max. 0.031 max. 0.0040.004 0.071 max. 0.061 0.3030.012 0.220 0.043 0.005 0.050 (t.p.) p20gm-50-300b, c-4 p3 3 +7 note each lead centerline is located within 0.12 mm (0.005 inch) of its true position (t.p.) at maximum material condition. d 0.40 0.016 +0.10 e0.05 k 0.20 0.008 +0.10 e0.05 l 0.60.2 0.024 0.10 e3 +7 e3 0.004 +0.008 e0.009 +0.004 e0.002 +0.004 e0.003 a c d g p detail of lead end f e b h i l k m j n m 110 11 20
56 m pd754202, 754202(a) 20 pin plastic shrink sop (300 mil) a 20 11 f b g e h k l 110 detail of lead end j i 3 +7 ? m m d n p20gm-65-300b-2 item millimeters inches a b c d e f g h i j k 7.00 max. 0.65 (t.p.) 2.0 max. 1.7 8.1 0.3 0.575 max. 0.276 max. 0.005 0.003 0.079 max. 0.319 0.012 0.240 0.008 0.023 max. note l m 0.12 0.5 0.2 1.0 0.2 6.1 0.2 0.005 0.020 +0.008 ?.009 each lead centerline is located within 0.12 mm (0.005 inch) of its true position (t.p.) at maximum material condition. 0.039 0.067 0.026 (t.p.) 0.15 +0.10 ?.05 0.006 +0.004 ?.002 n 0.10 0.004 0.012 +0.004 ?.005 0.30 0.10 0.125 0.075 +0.009 ?.008 c
57 m pd754202, 754202(a) 15. recommended soldering conditions the m pd754202 should be soldered and mounted under the following recommended conditions. for the details of the recommended soldering conditions, refer to the document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended below, contact your nec sales representative. table 15-1. surface mounting type soldering conditions m pd754202gs- -ba5 : 20-pin plastic sop (300 mil, 1.27-mm pitch) m pd754202gs- -gjg : 20-pin plastic shrink sop (300 mil, 0.65-mm pitch) m pd754202gs(a)- -ba5 : 20-pin plastic sop (300 mil, 1.27-mm pitch) m pd754202gs(a)- -gjg : 20-pin plastic shrink sop (300 mil, 0.65-mm pitch) soldering method soldering conditions symbol infrared reflow package peak temperature: 235 c, reflow time: 30 seconds or below ir35-00-2 (at 210 c or higher), number of reflow processes: twice or less vps package peak temperature: 215 c, reflow time: 40 seconds or below vp15-00-2 (at 200 c or higher), number of reflow processes: twice or less wave soldering solder temperature: 260 c or below, flow time: 10 seconds or below, ws60-00-1 number of flow processes: 1 preheating temperature: 120 c or below (package surface temperature) partial heating pin temperature: 300 c or below, time: 3 seconds or below (per side of device) caution do not use different soldering methods together (except for partial heating).
58 m pd754202, 754202(a) appendix a. m pd754202, 75f4264 function list item m pd754202 m pd75f4264 note program memory mask rom flash memory 0000h-07ffh 0000h-0fffh (2048 8 bits) (4096 8 bits) data memory static ram 000h-07fh (128 4 bits) eeprom tm none 400h-43fh (32 8 bits) cpu 75xl cpu general-purpose register (4 bits 8 or 8 bits 4 ) 4 banks instruction execution time ? 0.95, 1.91, 3.81, 15.3 m s (system clock: at 4.19-mhz operation) ? 0.67, 1.33, 2.67, 10.7 m s (system clock: at 6.0-mhz operation) i/o port cmos input 4 (on-chip pull-up resistor can be connected by mask option) cmos input/output 9 (on-chip pull-up resistor can be specified by software) total 13 system clock oscillator ceramic/crystal oscillator boot time after reset 2 17 /f x or 2 15 /f x 2 15 /f x (selected by mask option) timer 4 channels ? 8-bit timer counter: 3 channels (can be used for 16-bit timer counter) ? basic interval timer/watchdog timer: 1 channel a/d converter none ? 8-bit resolution 2 channels (successive approximation register) ? operable v dd = 1.8 v or higher programmable threshold port none 2 channels vectored interrupt external: 1, internal: 4 external: 1, internal: 5 test input external: 1 (key return reset function provided) supply voltage v dd = 1.8 to 6.0 v operating ambient temperature t a = C40 to +85 ?c package ? 20-pin plastic sop ? 20-pin plastic sop (300 mil, 1.27-mm pitch) (300 mil, 1.27-mm pitch) ? 20-pin plastic shrink sop (300 mil, 0.65-mm pitch) note under development
59 m pd754202, 754202(a) appendix b. development tools the following development tools are provided for system development using the m pd754202. in the 75xl series, the relocatable assembler which is common to the series is used in combination with the device file of each product. language processor ra75x relocatable assembler host machine part number os supply media (product name) pc-9800 series ms-dos tm 3.5-inch 2hd m s5a13ra75x ver. 3.30 to 5-inch 2hd m s5a10ra75x ver. 6.2 note ibm pc/at tm and refer to 3.5-inch 2hc m s7b13ra75x compatible machines os for ibm pc 5-inch 2hc m s7b10ra75x device file host machine part number os supply media (product name) pc-9800 series ms-dos 3.5-inch 2hd m s5a13df754202 ver. 3.30 to 5-inch 2hd m s5a10df754202 ver. 6.2 note ibm pc/at and refer to 3.5-inch 2hc m s7b13df754202 compatible machines os for ibm pc 5-inch 2hc m s7b10df754202 note ver. 5.00 or later have the task swap function, but it cannot be used for this software. remark operations of the assembler and device file are guaranteed only on the above host machines and oss.
60 m pd754202, 754202(a) debugging tool the in-circuit emulators (ie-75000-r and ie-75001-r) are available as the program debugging tool for the m pd754202. the system configurations are described as follows. hardware ie-75000-r note 1 in-circuit emulator for debugging the hardware and software when developing applica- tion systems that use the 75x series and 75xl series. when developing a m pd754202, the emulation board ie-75300-r-em and emulation probe ep-754144gs-r that are sold separately must be used with the ie-75000-r. by connecting with the host machine, efficient debugging can be made. it contains the emulation board ie-75000-r-em which is connected. ie-75001-r in-circuit emulator for debugging the hardware and software when developing applica- tion systems that use the 75x series and 75xl series. when developing a m pd754202, the emulation board ie-75300-r-em and emulation probe ep-754144gs-r which are sold separately must be used with the ie-75001-r. by connecting with the host machine, efficient debugging can be made. ie-75300-r-em emulation board for evaluating the application systems that use a m pd754202. it must be used with the ie-75000-r or ie-75001-r. ep-754144gs-r emulation probe for the m pd754202. it must be connected to ie-75000-r (or ie-75001-r) and ie-75300-r-em. it is supplied with the 20-pin flexible boards ev-9500gs-20 (compatible with 20-pin plastic shrink sop) and ev-9501gs-20 (compatible with 20-pin plastic sop) which facilitate connection to a target system. software ie control program connects the ie-75000-r or ie-75001-r to a host machine via rs-232-c and centronics i/f and controls the ie-75000-r or ie-75001-r on a host machine. host machine part number os supply media (product name) pc-9800 series ms-dos 3.5-inch 2hd m s5a13ie75x ver. 3.30 to 5-inch 2hd m s5a10ie75x ver. 6.2 note 2 ibm pc/at and refer to 3.5-inch 2hc m s7b13ie75x compatible machines os for ibm pc 5-inch 2hc m s7b10ie75x notes 1. maintenance product 2. ver. 5.00 or later have the task swap function, but it cannot be used for this software. remark operation of the ie control program is guaranteed only on the above host machines and oss. ev-9500gs-20 ev-9501gs-20
61 m pd754202, 754202(a) os for ibm pc the following ibm pc oss are supported. os version pc dos tm ver. 5.02 to ver. 6.3 j6.1/v note to j6.3/v note ms-dos ver. 5.0 to ver. 6.22 5.0/v note to j6.2/v note ibm dos tm j5.02/v note note only english mode is supported. caution ver. 5.0 or later have the task swap function, but it cannot be used for this software.
62 m pd754202, 754202(a) appendix c. related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. device related documents document name document number japanese english m pd754202, 754202(a) data sheet u12181j this document m pd754202 users manual u11132j u11132e 75xl series selection guide u10453j u10453e development tool related documents document name document number japanese english hardware ie-75000-r/ie-75001-r users manual eeu-846 eeu-1416 ie-75300-r-em users manual u11354j u11354e ep-754144gs-r users manual u10695j u10695e software ra75x assembler package users manual operation eeu-731 eeu-1346 language eeu-730 eeu-1363 other related documents document name document number japanese english ic package manual c10943x semiconductor device mounting technology manual c10535j c10535e quality grades on nec semiconductor devices c11531j c11531e nec semiconductor device reliability/quality control system c10983j c10983e electrostatic discharge (esd) test mem-539 C guide to quality assurance for semiconductor devices c11893j mei-1202 microcomputer product series guide u11416j C caution these documents are subject to change without notice. be sure to read the latest documents for designing, etc.
63 m pd754202, 754202(a) [memo]
64 m pd754202, 754202(a) notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools includ- ing work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immedi- ately after power-on for devices having reset function.
65 m pd754202, 754202(a) nec electronics inc. (u.s.) santa clara, california tel: 800-366-9782 fax: 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. sao paulo-sp, brasil tel: 011-889-1680 fax: 011-889-1689 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j96. 8
2 m pd754202, 754202(a) eeprom is a trademark of nec corporation. ms-dos is either a registered trademark or a trademark of microsoft corporation in the united states and/ or other countries. ibm dos, pc/at, and pc dos are trademarks of international business machines corporation. the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96.5

▲Up To Search▲

Price & Availability of UPD754202GSA

	To Download UPD754202GSA Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .